1. Field of the Invention
The present invention relates to a field effect transistor having a vertical channel which uses, for example, a nitride semiconductor and to a manufacturing method for the field effect transistor. This field effect transistor can be applied to, for example, high-power transistors used in power supply circuits of consumer electronics and to high-frequency transistors used in transmitting and receiving circuits of cellular telephones, extremely high-frequency radars, and the like.
2. Background Art
Group III nitride compound semiconductors represented by GaN have characteristics in that since the band gaps of GaN and AlN are as high as 3.4 eV and 6.2 eV at room temperature respectively, they have high breakdown electric field strength and that the saturated drift velocity of their electrons is high when compared with that of compound semiconductors such as GaAs or Si semiconductors. Because of this, the group III nitride compound semiconductors are expected to be used for high-voltage, high-power electronic devices and are being researched and developed extensively.
Besides, at the AlGaN/GaN hetero-interface, free electron are generated at their hetero interface by spontaneous polarization and piezo polarization perpendicular to the (0001) plane, thereby a sheet carrier concentration of 1×1013 cm−2 or higher can be achieved even when they are not doped. Because of this, reported Group III Nitride high-power or high-frequency transistors are heterojunction field effect transistors taking advantage of the inherent high density of two-dimensional electron gas at the hetero interface.
In such a horizontal channel transistor structure, there needs to secure a sufficient distance between a gate and a drain to increase the breakdown voltage. Because of this, when the horizontal channel transistor structure is applied to large-current transistor, problems arise in that their chip area is increased and it is difficult to produce them at low cost.
As a device structure by which a large-current device with a smaller chip area can be realized, there is a transistor with a vertical structure which is called “PBT” (permeable base transistor) or “SIT” (static induction transistor).
In Si semiconductors, a mesa structure, that is, a structure in which a source electrode and a drain electrode are formed on the upper stage and lower stage of a convex structure respectively, a gate electrode is formed on the sidewall of the upper stage of the convex structure, and a channel current is controlled by a gate voltage applied to the gate electrode has been proposed and it characteristics have been recognized (see Electron Devices, 47(2000) 482, by J. Nishizawa et al., IEEE Trans.). Moreover, for the transistor with the vertical structure using a group III Nitride semiconductor, its structural proposition and results of its device simulation have been reported.
An example of structures of heretofore reported field effect transistors with vertical structures (PBTs) using group III Nitride semiconductors will be described below.
FIG. 13 is a cross-sectional view of a structure of a conventional vertical channel transistor using a group III Nitride semiconductor. In FIG. 13, reference numeral 1301 denotes a first n+-type GaN layer, reference numeral 1302 a n−-type GaN layer, reference numeral 1303 a second n+-type GaN layer, reference numeral 1304 a drain electrode, reference numeral 1305 a gate electrode, and reference numeral 1306 a source electrode.
In the vertical channel transistor, the first n+-type GaN layer 1301 is formed on the drain electrode 1304 and on the layer 1301, the n−-type GaN layer 1302 with a convex structure is formed. As shown in FIG. 13, the gate electrode 1305 is formed so that the electrode 1305 contacts the lower stage and the sidewall of the upper stage of the convex structure. The second n+-type GaN layer 1303 is formed on the upper stage of the convex structure and on the layer 1303, the source electrode 1306 is formed.
In this vertical channel transistor, a current flowing between the source and the drain is controlled by a voltage to the gate electrode 1305, thereby a field effect transistor can be realized (see Electron Device Letters, 23(2002) 303, by V. Camarchia et al., IEEE).
For this structure, there is a report on the simulation results of its device characteristics. In this report, to achieve sufficient pinch-off characteristics, the width of the upper stage of the convex structure is set at about 0.2 μm and in the field effect transistor, the thickness of its gate electrode is set at 20 nm. Such a structure realizes, a very small-area high-power transistor with a high current density and a low on resistance.
However, in the vertical channel field effect transistor shown in FIG. 13, the area of the source electrode formed on the upper stage of the convex structure is small. Besides, the group III nitride semiconductors have large band gaps and generally have high electrode contact resistance, which makes the series resistance of transistors very high. As a result, reduction of the on resistance is limited by the large electrode contact resistance.